3-D semiconductor die stacking is an emerging and exciting technology which offers lower power consumption, reduced form factor and interface latency with improved bandwidth. A lot of research is underway to improvise the electrical performance of multi-stacked die chips including reliability at both the package and board-level. A majority of the benefit from multi-die stacking comes from the reduction in wire delays across chips, which in turn results in reducing the latency, power consumption and with an increase in the bandwidth.
The Through Silicon Vias (TSVs) in a 3-D stack are the channels for transferring signals between different tiers in a 3-D stack. The functionality of a 3-D integrated circuit strongly depends on the fidelity of signals through TSVs. Defects can be created in the TSV process while forming the TSVs before bonding (assuming a via-first process) or while bonding different dies together. Specifically, TSVs are susceptible to short defects. A short during TSV formation creates a resistive defect through the oxide. Since the substrate surrounding the TSVs is strongly connected to ground, this results in a low resistive path between the TSV and ground. Such shorts in the TSV will result in partial or complete degradation of signal quality. When the TSV is driven by a driver, the signal swing and/or slew at the receiver end can vary significantly resulting in either complete or partial signal degradation. Therefore, maintaining the signal fidelity through TSVs, especially on critical interfaces such as high speed serial links which establish communication in a system on a chip, is a primary challenge in 3-D system integration. TSV technology drives the integration of chips in 3-D packaging and overall integrated circuit reliability depends on TSVs and therefore it is important for TSVs to be free from defects.
Micro C4 (μC4) bumps are solder bumps used to form connections between two semiconductor dies. TSVs and μC4 bumps are often used together to form the interconnecting structure between two semiconductor dies. A signal traveling from a first semiconductor die to a second die travels through a TSV and a μC4 bump to reach the second die, which may result in signal propagation time delays.